In this role you will be responsible for taking part in SoC verification process of next-generation WiFi chip in a fast growing startup company.
You will define a verification test plan for System Verilog UVM verification environment, define coverage metrics, architect and implement verification environment including the integration of existing verification IPs.
- Above 3 years’ experience in UVM, VMM or E (Specman) – mandatory (At least 1 year with UVM)
- BSc / MSc. in Electronics Engineering from a known university
- Experience in development of Sub-System Verification Environments involving different IPs
- Substantial experience with verification methodologies (Reusable/Random Based/Coverage Driven)
- Very good debugging skills
- Good Verilog skills
- Good C skills is an advantage
- Highly motivated person. Ability to get into a complex Verification Environment and own it
- Quick learner
- Knowledge with 802.11 MAC is a big advantage.
- Very good human relations